1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g., a semiconductor memory device including a static memory cell.
2. Description of the Related Art
Recently, a static random access memory (SRAM) using the hierarchical bit line method is beginning to be used as the degree of micropatterning and the operating speed of SRAMs increase. This SRAM using the hierarchical bit line method comprises a plurality of memory cell arrays, a local sense amplifier for reading data from each memory cell array, and a global sense amplifier for inputting data to and receiving data from each local sense amplifier.
That is, a plurality of local bit lines whose bit line capacitance is reduced by finely dividing a bit line are connected to a plurality of local sense amplifiers. Each local sense amplifier amplifies data and sends the amplified data to a global bit line, and a global sense amplifier connected to the global bit line decides the data. In this manner, data is read from a memory cell by the two stages of bit lines/sense amplifiers. The cell current can be reduced because the capacitance of each bit line can be reduced by thus hierarchizing the bit lines.
A memory cell array placed on the far side of the local sense amplifier from the global sense amplifier has a replica cell for controlling the activation timing of the local sense amplifier. That is, a line delay equal to that occurring when accessing a memory cell farthest from the global sense amplifier is reproduced using the replica cell, and the local sense amplifier is controlled using the timing of a signal generated by this replica cell.
Note that as a related technique of this kind, a technique that readily optimizes the operation timing in a static semiconductor memory device using a dummy memory cell is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2004-71118).